As integrated circuits continue to become more complex and consume more power, the problem of keeping a constant voltage across the entire integrated circuit (IC) is increasingly difficult. In particular, it is hard to ensure a constant voltage in design and even harder to predict in simulation. For example, instruction dependent voltage droops, i.e., those caused by instructions that consume resources sufficient to cause a voltage droop, are difficult to predict. Furthermore, conventional static timers used for simulation typically assume constant voltage, which causes false critical path predictions. The effect of these local or global voltage droops is that the maximum frequency of the IC is reduced.
There are several known approaches to this problem. In one approach, attempts are made to eliminate voltage droop fails by testing the IC under worst case voltage droop scenarios and decreasing the maximum frequency rating so that the part will not fail for a customer. This approach however oftentimes results in unnecessary maximum frequency rating reductions, e.g., of up to 140 MHz. In another approach, circuitry to sense voltage droops and reduce the IC frequency dynamically is used. Unfortunately, this latter approach is not very practical for situations with a fixed microprocessor to bus frequency ratio.
There is a need in the art for a solution that does not suffer from the problems of the related art.